EDN

A practical approach to reusing HDL code in FPGA designs

From the very first day that you learn a new hardware description language (HDL), you reuse code. Initially, this might involve copying an example and modifying it in order to learn and expand your ...
Business Wire

InterMotion Technology Boosts IP Verification Productivity for Lattice Semiconductor’s CrossLink FPGA Family Using Aldec’s Active-HDL

HENDERSON, Nev.--(BUSINESS WIRE)--Aldec, Inc., a pioneer in mixed-HDL language simulation and hardware-assisted verification for FPGA and ASIC designs, today announced that InterMotion Technology has ...
WatersTechnology

Impulse Announces C-to-HDL FPGA Compiler

Impulse Accelerated Technologies has announced the latest version of its C-to-HDL compiler, providing field-programmable gate array (FPGA) coding support for Arista Switch users. FPGAs, which are ...
Semiconductor Engineering

HDL Simulation Acceleration Solution For Microchip FPGA Designs

A way to accelerate a HDL simulation for a system FPGA design that includes the custom logic and reused IP cores where the testbench executes in the simulator and the synthesizable parts of the design ...
EDN

Mentor improves HDL suite for ASIC, FPGA designs

SAN MATEO, Calif.—Mentor Graphics Corp. has enhanced its HDL Designer Series front-end design suite to provide better ways to create and manage hardware description languages in ASIC and FPGA designs.
TechRepublic

FPGA Implementation of Interrupt Controller (8259) by Using Verilog HDL

A priority interrupt controller is a hardware designed chip which acts as an overall system manager to efficiently handle the multiple interrupts that tend to occur from the varied number of ...