IMG DXS delivers 1.5x the peak performance of our previous generation of automotive GPUs, setting a new benchmark in safe computing that outperforms competitor equivalents. Its revolutionary ...

This 2MS/s 16bit ADC is a high accuracy low power data converter for rail-to-rail input signal. It supports single-ended and differential input mode. Calibration is applied to enhance the ADC ...

Synopsys UCIe PHY IP enables high-bandwidth, low-power, and low-latency die-to-die connectivity in a multi-die package for hyperscale data center, AI, and networking applications. The PHY’s flexible ...

This is the first IP from SiFive to include a highly scalable AI matrix engine, which accelerates time to market for ...

Demonstrations highlighting leadership in PCIe over Optics, Ethernet, PCIe and UCIe SerDes on 3nm TSMC CoWoS packaging. Dr.

RaaS’s mission is to provide access as a service to the most advanced semiconductor technology (Research as a Service). RaaS ...

1. PHY IP for vehicle Ethernet 100 and 1000base-t1 2. PHY IP of on-board Ethernet 100 and 1000base-t1 3. MAC IP of vehicle Ethernet 4. SWITCH IP of the vehicle Ethernet ...

A 125KHZ low-frequency transmitter chip on the car (DC-DC, LF drive, IMMO function, external interrupt, external crystal oscillator, etc.) needs to support 48V platform, and IO voltage needs to ...

In a significant achievement for the automotive industry, Cadence's Tensilica HiFi 5 Digital Signal Processors (DSPs) are now ...

The Digital Blocks DB-SPI-MS is a Serial Port Interface (SPI) Controller Verilog IP Core supporting both Master/Slave SPI Bus transfers. The DB-SPI-MS contains an AMBA AXI, AHB, or APB Bus Interface .

Intel to Produce Custom AI Fabric Chip on Intel 18A and Custom Xeon 6 Chip on Intel 3 for AWS; Multi-Year, ...

With RISC-V processor architectures gaining traction across diverse computing systems, ensuring their reliability through ...